A conventional RMG process flow typically involves separate stages for gate processing, source/drain processing, and contact formation. The number of stages in such complex integration flows jeopardizes process uniformity and device yield. For instance, a conventional RMG front-end flow for a fin field effect transistor (FINFET) may include (i) a fin and shallow trench isolation (STI) module, (ii) a dummy gate module, (iii) a spacer module, (iv) source/drain processing steps, (v) an insulator encapsulation step followed by a poly exposure and pull step (hereinafter referred to as Poly-Open-Chemical-Mechanical-Polishing (Poly-Open-CMP) module), and (vii) a replacement high-K/metal gate (HK/MG) module. The integration of each module becomes more challenging in each node due to scaling according to Moore's Law. The incorporation of new performance elements such as a low-K dielectric spacer tends to make the integration even more complex from one technology node to the next. In particular, the need for gate length scaling increases the complexity of RMG module substantially along with the engineering of various metal gate stacks with appropriate work function.
A need therefore exists for methodology enabling a simplified and robust RMG process integration with reduced variability.